In today’s world technology changes fast and in an era where everyone has a mobile device there are larger SOC’s that require less and less power but more graphical features. Handling today’s floor plans is very challenging with the size and complexity features of the designs.  

Some designs require feed thru portions for an abutted design while channel base allows for complex voltage requirements and closure faster for block level design. There are arguments for both and in some cases, both are needed in a design.  

Sintegra understands both of these design styles and the challenges that come with both and can drive all aspects of these types of designs.  


Here are a few challenges we address along with many others:

  • Hierarchical block partitioning (create appropriate sized blocks)

  • Pin placement (placement driven using connectivity based)

  • Feed-thru modules and routes

  • Clock distribution and gating

  • Routing layer assignment for critical nets

  • Power planning for Voltage Areas

  • IO block placement and planning (ie DDR, EMMC)​​ 


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