The days of just placing macros on the edges and tuning some areas of congestion are gone. Designs today are very complex, especially for low power.
At smaller process nodes monitoring devices are also needed to track the process. At Sintegra we are low power aware which means we look at power switches, level shifters, state retention, always on feed-through cells, isolation cells, power enables, and power grids. Rules for DRC checks are considered as well for spacing of cells and pin placement for clocking and power.
Sintegra understands the needs for good timing constraints while placing the cells for a design. Alignment cells and metal stepping only cells are also considered in the initial placement in anticipation of possible changes after base layer freeze.
Sintegra has strong knowledge in optimizing for large designs using parallel processing and optimization techniques. Maximizing efforts on large machines using many threads to complete large blocks much faster while still maintaining good Quality of Results (QOR).