Timing Constraints​

In a SOC world now dominated by low power and massive functionality, it takes many clocks in a design to achieve the desired platform.  Once a couple of clocks were all you needed and now you may have several hundreds of clocks for a design.  Key fundamentals to proper synthesis (not over optimized) is a good timing setup.  This then holds true for physical design as well.  

 

Achieving those goals is what Sintegra really understands. Working with Static timing tools and driving a good synthesis result and especially using topology-based when available provides a low power design that meets the timing requirements.  Here are some key items Sintegra will help with:

• Create proper io timing for block partitioning (60/40 starting point then refine)

• Identifying Multi-cycle or false paths

• Use of multi-mode and multi-scenario to help define the design

• Identifying High Fanout Logic

• Specifying clock latency numbers to balance timing

• Use of multi clocks through single inputs

• Signal Integrity setup and checking

• Latency balancing between io and internal logic

• Designing to meet advanced rule checks (clock trans vs std cells)